1. Field of the Invention
The present invention relates to a method for controlling an unreliable data transfer in a data channel. Further, the present invention relates to an apparatus for controlling an unreliable data transfer in a data channel.
2. Description of the Related Art
In an arbitrary data transfer channel between a transmitting unit and a receiving unit errors may occur. The detection and correction of said errors requires a lot of time. In particular, if a central processing unit of a processor system fetches data from higher level caches, then data will be delivered with different latencies. Said latencies depend on the cache level. For performance reasons, a fast response is preferred. For data integrity reasons, an error-free data transfer is required. Higher level caches are physically far away from lower level caches or from the central processing unit itself. Higher level caches have longer latencies.
Long data transfer from one cache level to another cache level are more susceptible to transient and permanent errors at interfaces, transfer hardware, data buses or the like. Said long data transfer is also performed over chip boundaries. Error checking and correcting hardware have significant additional delay effect on the overall transfer latency.
In known systems there is either an optimal tradeoff checking and correcting overhead or a rich system performance. The main problem of known systems is a design decision and a static implementation for the benefit of a fast data throughput or a reliable data transfer. The speed-optimized data transfer systems have the drawback of poor checking features and thus a potential data integrity problem. The fail-save data transfer has the drawback of poor system performance.
The article “Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection” by Boris Polianskikh and Zeljko Zilic (Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL'02), 2002), incorporated herein by reference, relates to single-error-correcting and double-error-detecting in multi-level dynamic random access memories.
The article “Comparison of Duplex and Triplex Memory Reliability” by Nitin H. Vaidya (IEEE Transactions on Computers, Vol. 45, No. 4, April 1996, pp. 503-507), incorporated herein by reference, describes a classical approach in fail-save architectures.
The article “Selector-Line Merged Built-In ECC” by Junzo Yamada (IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pp. 868-873), incorporated herein by reference, deals with the optimization of checking and correcting circuits.
It is an object of the present invention to provide an improved method and apparatus for controlling an unreliable data transfer in a data channel.